The present invention relates to a technique of predicting LSI property degradation with time which results from a hot carrier phenomenon or the like, and of reflecting the prediction in LSI timing simulation.
A semiconductor integrated circuit (hereinafter referred to as LSI) has a certain life and suffers from failures or poor operation after a certain time period of operation. The main causes of such failures and poor operation include property degradation due to a hot carrier phenomenon or the breaking of a wire due to electro-migration. Of these causes, the hot carrier phenomenon degrades the driving capability of a transistor, which causes the LSI operational timing to change with time, leading to a wrong operation.
The recent development of manufacturing technique has accelerated the micro-miniaturization of LSI devices, so that a strong electric field which is generated in the LSI devices promotes the evolution of a hot carrier, or a high energy electron. Consequently, it is becoming harder to secure the LSI reliability against the hot carrier phenomenon.
In order to secure the LSI reliability, it is possible to provide an appropriate margin to the operational timing of every circuit uniformly so that sufficient allowance is made for changes in the operational timing with time, thereby securing the operation for a certain period of time. However, in this method, the margin is set in preparation for the worst case, which tends to make an LSI specification excessively reliable. Since the reliability and performance of an LSI are in the relation of the trade-off, the provision of excessive reliability leads to a decrease in the performance. Thus, it has been difficult to accomplish a high-performing LSI by this method.
In order to solve this problem, the following method has been used. The values of predetermined operational conditions at the operation of an LSI are examined for each circuit cell which is a circuit unit for composing the LSI, and it is verified whether the values of the operational conditions for each circuit cell fall in the range of satisfying the predetermined target values of the degradation amount or life of the LSI. Here, the circuit cell refers to an inverter which belongs to a standard cell library and which is used in an integrated circuit intended for a special purpose (ASIC) or the like. A circuit cell whose degradation amount and life do not satisfy the target values is regarded as a problematic circuit cell with regard to LSI reliability, and such a measure as design modification is taken.
However, this conventional method verifies only the degradation amount and life for each circuit cell composing an LSI, which tends to make the LSI specification excessively reliable. This point will be detailed as follows.
An LSI usually operates in accordance with a predetermined operational frequency. In other words, the predetermined time period determined by the predetermined operational frequency becomes a unit for process time in an LSI. On the other hand, signals in an LSI run through a signal path which is composed of several circuit cells within the predetermined time period. If a signal propagation delay in the signal path is so extended by degradation as to exceed the predetermined time period, then the LSI operational timing becomes out of order, leading to a wrong operation. Conversely, the LSI operational timing is maintained in order without causing a wrong operation as long as the extension of the signal propagation delay in a signal path due to degradation does not exceed the predetermined time period.
Suppose that there are signal paths A and B, and the signal path A has a signal propagation delay which is approximately equal to the predetermined time period (that is, susceptible to delay degradation), whereas the signal path B has a signal propagation delay much smaller than the predetermined time period (that is, resistant to delay degradation). In addition, suppose that both the signal paths A and B include circuit cells which have the common operational condition values, and that the values do not fall in the range of satisfying the target values of the degradation amount and life.
Under these conditions, according to the conventional method, the circuit cells included in the signal paths A and B are regarded as problematic circuit cells with regard to LSI reliability, and become the objects of design modification or the like. However, in actuality, the circuit cells included in the signal path A which is susceptible to delay degradation should be regarded as problematic, but the circuit cells included in the signal path B which is resistant to delay degradation should be judged not problematic with regard to the LSI reliability.
Thus, whether a circuit cell becomes problematic or not with regard to LSI reliability differs one circuit cell from another even under the same operational conditions. This is because the range of the degradation amount and life permitted to each circuit cell differ depending on the positions of the circuit cells in the LSI signal flow.